For the mask ROM, the memory data are loaded in the memory cells during manufacture. The data writing step is called programming or coding. Usually, the interval from the time when the coding data in the mask ROM are obtained from the user to the time of shipment of the product is called to cycle time, or TAT (turnaround time). For the ROM products, shortening the TAT is an important task from the viewpoint of the commercial value of the products and productivity.
Depending on the data coding method, the mask ROMs can be classified into the diffusion type, contact type and via contact type. For each of these methods, there is a trade-off relationship between the cycle time and the degree of integration. When the actual ROM products are manufactured, it is necessary to select the appropriate method corresponding to the characteristics and demands on the specific type of products.
FIG. 7 is a schematic cross-sectional view illustrating the concept of the mask ROM formed using the diffusion method.
In FIG. 7, 1 represents p.sup.- substrates or p.sup.- wells; 2-1, 2-2, 2-3, 2-4, 2-5 and 2-6 represent the n.sup.+ diffusion layers; 3-1, 3-2a, 3-3, 3-4a, and 3-5 represent insulating films; 4-1, 4-2, 4-3, 4-4, and 4-5 represent polysilicon films; and 5-1, 5-2, 5-3, 5-4, 5-5, and 5-6 represent metal wiring layers.
For example, insulating films 3-1, 3-2a, 3-3, 3-4a, and 3-5 may be made of silicon oxide film (SiO.sub.2).
n.sup.+ diffusion layers 2-1, 2-2, 2-3, 2-4, 2-5, and 2-6 are connected through contacts to metal wiring layers 5-1, 5-2, 5-3, 5-4, 5-5, and 5-6.
In addition, n.sup.+ diffusion layers 2-1, 2-3, and 2-5 are grounded through metal wiring layers 5-1, 5-3, and 5-5 connected to them, respectively.
Polysilicon films 4-1, 4-2, 4-3, 4-4, and 4-5 are connected commonly to wiring not shown in the figure, and the wiring forms the word lines.
Also, metal wiring layers 5-2, 5-4, and 5-6 are connected to the bit lines, respectively.
For the diffusion type mask ROM of this invention, data coding is performed, for example, by means of oxidation processing at the periphery of the oxide film underneath a polysilicon film in order to set a large film thickness of the gate oxide film on a level with little function as transistors.
As shown in FIG. 7, for example, a gate transistor is formed from polysilicon film 4-1 and n.sup.+ diffusion layers 2-1 and 2-2 beneath the two sides of gate oxide film 3-1. When a high-level voltage is applied to polysilicon film 4-1 as gate, a channel is formed in the substrate region below gate oxide film 3-1. Consequently, the ON/OFF state of the transistor is under control corresponding to the voltage applied to gate 4-1.
On the other hand, for oxide film 3-2a underneath polysilicon film 4-2, as aforementioned, the film thickness is increased by means of oxidation processing. Consequently, even when a high voltage is applied to polysilicon film 4-2, there is still no channel formed in the substrate region below oxide film 3-2a, so that a transistor cannot be formed from polysilicon film 4-2 and n.sup.+ diffusion layers 2-2 and 2-3 formed in the substrate below the two sides of the polysilicon film.
Depending on whether a transistor is formed or not, the potential of the bit line is determined during reading. By detecting the bit line potential with a sense amplifier, it is possible to read the memory data in the memory cells of the mask ROM.
For such diffusion type mask ROM, data coding is performed by performing or not performing the oxidation processing for the periphery of the oxide film below the polysilicon layer. Consequently, the memory cells of the mask ROM formed can be made smaller, that is, the degree of integration of the memory can be increased. This is an advantage.
However, for the aforementioned mask ROM formed using the conventional diffusion method, as data coding is performed during the step of formation of the polysilicon layer, many steps of operation must be performed after coding and before formation of the mask ROM, and the cycle time becomes longer. This is a disadvantage.
On the other hand, when the mask ROM is formed using the contact method or via contact method, data coding is performed before the step of formation of the metal wiring layer. Consequently, before obtaining the coding data, it is possible to perform the manufacturing process for the polysilicon layer and the layers on it, such as the first or second metal layers if the process pertains to a 3-layer metal wiring operation. As a result, the cycle time of the manufacturing operation can be significantly shortened than that in the diffusion method. This is an advantage. In practice, the cycle time in manufacturing the mask ROM is only a fraction (1/10-1/5) of that of the diffusion method.
However, for the contact method or via contact method, while the cycle time can be shortened, the area occupied by each memory cell is nevertheless larger, that is, the degree of integration is lower, and the chip area is larger for the mask ROM with the same capacity. This is a disadvantage.
Consequently, when a high degree of integration is demanded, the diffusion method is adopted. In this case, the manufacturing cycle time becomes longer and the production efficiency goes down. On the other hand, when a shorter manufacturing cycle time is demanded, while there is certain margin for the demand on the degree of integration, the contact or via contact method is adopted.
Consequently, there is a demand for development of a type of high-performance mask ROM that has both the advantages of the diffusion type mask ROM and the advantages of the contact or via contact type mask ROM, that is, with both a shorter manufacturing cycle time and a high degree of integration.
The purpose of this invention is to solve the aforementioned problems of the conventional technology by providing a type of mask ROM which can minimize the increase in the area of the memory cells while shortening the manufacturing cycle time.